Internship/Thesis: Developing an Eclipse plugin (Java) for the UVM template generator

For generation of SystemVerilog UVM test environments, DMOS GmbH uses a template-based generator. The edition of test sequences incorporates the IDE Eclipse. Subject of the project is to develop a plugin for Eclipse (using Java) which integrates the template generator into the Eclipse environment. Furthermore, the plugin should be extended in order to offer text formatting and autocomplete features for SystemVerilog.

During this internship/thesis the following tasks are to be solved

  • Familiarize with the existing project structure
  • Develop a plugin for Eclipse that integrates the SystemVerilog template generator
  • Integrate text formatting and autocomplete features

Our Requirements

  • Completed basic course of Electrical Engineering, Informatics or Information Systems Technology
  • Experiences in Object Oriented Programming with Java
  • Basic knowledge of SystemVerilog

This is what you will benefit of

  • Equitable Remuneration
  • Interesting and challenging tasks in an international environment
  • Competent co-workers 
  • Flexible working time, possibility of Mobile-Office, company and social events

Apply for it! Send us your application as PDF-File by Mail. We are looking forward to get to know you in person!

Bergstraße 4
D-01069 Dresden
Tel.: 0351 / 479 42 – 0

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