Internship: Support for verification in digital design
During this internship/thesis the following tasks are to be solved
- Familiarization and further development of our verification methods
- Development and implementation of verification strategies
- Documentation of the results
Our Requirements
- Completed basic studies in electrical engineering, information systems engineering (or comparable).
- Experience in the programming languages VHDL, Verilog and C
- Experience in the SystemVerilog language and the UVM verification method is an advantage
- Experience in the use of simulation tools
- Basic knowledge of digital design for ICs and FPGAs
This is what you will benefit of
- equitably remuneration
- Interesting and challenging tasks in an international environment
- Comprehensive introductory and training programs
- Competent co-workers
- Flexible working hours, possibility of mobile office, company events and social offers
Interested?
Apply for it! Send us your application as PDF-File by Mail. We are looking forward to get to know you in person!
Contact
DMOS GmbH
Bergstraße 4
D-01069 Dresden
Tel.: 0351 / 479 42 – 0
dmos-bewerbungen@dmos2002.de
www.dmos2002.de
Download the job offer as PDF
Download here
